There is continual pressure on the microelectronics industry to produce integrated circuits that are smaller, faster, and more powerful. As a part of the effort to produce such integrated circuits, the size of individual structures within the integrated circuits is constantly reduced. However, sometimes a desired reduction in size brings with it an attendant change in another property of the device which is not desired. For example, reducing the size of a MOS transistor is generally considered beneficial, as by so doing the number of transistors that can fit within a given geometry is increased, yielding an integrated circuit that is commensurately more powerful. However, as the transistor size is reduced, so also is the width of the gate generally reduced, which often leads to undesired changes in the electrical characteristics of the transistor.
One method of compensating for this undesired change in the electrical characteristics of the transistor is to design it with a gate that does not pass straight through the transistor, but takes a longer path through the transistor instead. Such designs are often referred to as bent gate transistors. One type of bent gate transistor is a forty-five degree bent gate transistor 12, such as depicted in FIG. 1. In this example, the bent gate transistor 12 is formed as part of an integrated circuit 10. The gate 14 has at one end a first straight region 16, a first corner region 18 with a nominal forty-five degree bend, a bent region 20, a second corner region 22 with a nominal forty-five degree bend, and a second straight region 24. In this manner, there is a greater width of the gate 14 within the transistor 12 than there would be if the gate just cut straight through the transistor 12.
Unfortunately, even though such bent gate transistors are commonly used in the microelectronics industry, they are not well characterized. By this it is meant that traditional integrated circuit modeling routines, such as SPICE, do not adequately predict the behavior of such transistors. Thus, bent gate transistors are typically either over-specified so as to ensure acceptable minimum operating characteristics, or tend to require a lengthy development cycle including many iterations of design optimization.
What is needed, therefore, is a method for modeling bent gate transistors so that the development cycle of integrated circuit designs employing such transistors can be reduced, and the final operating characteristics of the transistors can be better predicted.